搜索资源列表
DDR2_hardcore_userguide
- xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
user_design
- spartan3a-ddr2 (16bits 333M)
ddr2_sdram_latest[1].tar
- ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
dual
- DDR2双内存切换程序部分代码,用于VHDL的FPGA开发-DDR2 dual memory switching part of the program code for VHDL-FPGA development
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
DDR2_Control
- 本源码是用FPGA控制DDR2芯片的vhdl源码，并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code